Integrated circuits include field effect transistors (FETs) of different types, which are optimized in view of different requirements, for example, switching speed, on-resistance, threshold voltage conformity, leakage current and switching power. Some types of FETs are based on a 3D-channel. In the conductive state of a 3D-channel FET, a conductive inversion layer (channel) extends along more than one plane. Examples of 3D-channel FETs are FinFETs, EUDs (enhanced U-groove devices), RCATs (recess channel array transistors), and S-RCATs (sphere-shaped recess channel array transistors).
Shrinking down FETs in size, the off-state leakage current becomes a device characteristic of increasing relevance with regard to low-power and stand-by applications. One challenge for 3D-channel FETs is the gate induced drain leakage in the transistor off-state. An electrical field which is effective in the region of one of the pn-junctions between the respective source/drain region and the channel region may bend up the energy band for valence band electrons near the interface between the semiconductor substrate and the gate electrode such that electrons may tunnel from the valence band into the conduction band and may induce a leakage current that flows between the respective source/drain region and a semiconductor bulk above or in which a semiconductor body of the FET is formed.
A need exists for a method integrating the formation of different types of FETs including 3D-channel FETs and improving the FET characteristics, for example, ensuring a low gate induced drain leakage in 3D-channel FETs.
For these and other reasons, there is a need for the present invention.